1. Field of the Invention
The present invention relates to a manufacturing method for reducing the thickness of a dielectric layer. More particularly, the present invention relates to a manufacturing method for decreasing process time and reducing the thickness of a dielectric layer.
2. Description of the Related Art
FIGS. 1A through 1C are schematic, cross-sectional views showing the conventional manufacturing steps of MOS and capacitor. First, referring to FIG. 1A, a field oxide 102 is formed on a substrate 100 as a device isolation structure. A gate oxide layer 104 is then formed by thermal oxidation on the substrate 100, and the thickness of gate oxide layer 104 is about 100 angstroms to 200 angstroms. Next, a first polysilicon layer is deposited over the substrate 100. The first polysilicon layer is defined by photolithography and etching to form a gate 106 of a MOS on the gate oxide layer 104 and a bottom electrode 108 of a capacitor on the field oxide 102. Referring to FIG. 1B, an oxide layer 110 is formed by thermal oxidation on the gate 106 and on the bottom electrode 108. The oxide layer 110 is used as a capacitor dielectric layer. Referring to FIG. 1C, a second polysilicon layer is then deposited over the substrate 100 and defined by photolithography and etching to form an upper electrode 112 of the capacitor on the dielectric layer 110.
The conventional manufacturing method for forming the gate and the capacitor consumes a long cycle time of process to causes decreased efficiency and high cost, and it is difficult to use this method to form a thin dielectric layer to increase the capacitance.